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Freescale Semiconductor /MKW40Z4 /ZLL /SEQ_CTRL_STS

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Interpret as SEQ_CTRL_STS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLR_NEW_SEQ_INHIBIT)CLR_NEW_SEQ_INHIBIT 0 (EVENT_TMR_DO_NOT_LATCH)EVENT_TMR_DO_NOT_LATCH 0 (0)LATCH_PREAMBLE 0 (NO_RX_RECYCLE)NO_RX_RECYCLE 0 (0)FORCE_CRC_ERROR 0 (0)CONTINUOUS_EN 0XCVSEQ_ACTUAL 0 (SEQ_IDLE)SEQ_IDLE 0 (NEW_SEQ_INHIBIT)NEW_SEQ_INHIBIT 0 (RX_TIMEOUT_PENDING)RX_TIMEOUT_PENDING 0 (RX_MODE)RX_MODE 0 (TMR2_SEQ_TRIG_ARMED)TMR2_SEQ_TRIG_ARMED 0SEQ_T_STATUS0 (SW_ABORTED)SW_ABORTED 0 (TC3_ABORTED)TC3_ABORTED 0 (PLL_ABORTED)PLL_ABORTED

LATCH_PREAMBLE=0, FORCE_CRC_ERROR=0, CONTINUOUS_EN=0

Description

SEQUENCE CONTROL AND STATUS

Fields

CLR_NEW_SEQ_INHIBIT

Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway
EVENT_TMR_DO_NOT_LATCH

Overrides the automatic hardware latching of the Event Timer
LATCH_PREAMBLE

Stickiness Control for Preamble Detection

0 (0): Don’t make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register “sticky”, i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect

1 (1): Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register “sticky”, i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence
NO_RX_RECYCLE

Disable Automatic RX Sequence Recycling
FORCE_CRC_ERROR

Induce a CRC Error in Transmitted Packets

0 (0): normal operation

1 (1): Force the next transmitted packet to have a CRC error
CONTINUOUS_EN

Enable Continuous TX or RX Mode

0 (0): normal operation

1 (1): Continuous TX or RX mode is enabled (depending on XCVSEQ setting).
XCVSEQ_ACTUAL

Reflects the programmed sequence that has been recognized by the ZSM Sequence Manager
SEQ_IDLE

ZSM Sequence Idle Indicator
NEW_SEQ_INHIBIT

New Sequence Inhibit
RX_TIMEOUT_PENDING

Indicates a TMR3 RX Timeout is Pending
RX_MODE

RX Operation in Progress
TMR2_SEQ_TRIG_ARMED

indicates that TMR2 has been programmed and is armed to trigger a new autosequence
SEQ_T_STATUS

Status of the just-completed or ongoing Sequence T or Sequence TR
SW_ABORTED

Autosequence has terminated due to a Software abort.
TC3_ABORTED

Autosequence has terminated due to an TMR3 timeout
PLL_ABORTED

Autosequence has terminated due to an PLL unlock event

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data